# Arithmetic Logic Unit (ALU)

Probably the most common use of combinational logic is in the arithmetic logic unit. An arithmetic logic unit (ALU) is a functional unit that performs arithmetic (addition, subtraction, etc.) and logical (AND, OR, etc.) operations on integer binary numbers. It is also one of the most fundamental units of many computing circuits, including the central processing unit (CPU) of computers, and the graphic processing unit (GPU) of video cards. Individual ALUs can be highly specialized to certain logic operations, and an integrated circuit may include multiple ALUs.

An ALU has various inputs and various outputs. Inputs of an ALU are primarily the operands which are the data to be operated on. In addition, an ALU has opcodes (operation codes) as inputs to control the type of operation the ALU shall perform. A separate status input typically contains information about a previous operation. The output of an ALU is the result of the performed operation. In many designs, the ALU also has a status output that is either forwarded to other components of the ALU for further processing, or used as a status flag that indicates different conditions of an operation. For instance, if an ALU compares two numbers, a status flag can indicate whether both numbers are equal or unequal.

The diagram includes a small example of operations an ALU can perform. Some other very typical opcodes are ‘compare’, ‘increment’, ‘decrement’, ‘shift right’, ‘shift left’, ‘pass through’, and modulo function (an operation performed to check whether a number is even or odd). Modern ALUs feature more than 100 instruction opcodes.

Adding two binary numbers is done by aligning the numbers vertically from the least significant bit. If one bit number is shorter than the other, the shorter number is padded with leading zeros. Each bit position from one number is added to the same bit position of the other number, starting from the right and proceeding to the left. In principle, the addition is identical to an addition in the decimal system, the only difference is that ‘2’ must already be represented as a binary ’10’. So 0+0=0, 0+1=1, and 1+0=1. In case 1+1 are added, the sum is a binary 10, so the output for the least significant bit of the sum is 0 and a 1 is carried over one position to the left for further addition.

The circuit that can perform the addition for the least significant bits of two binary numbers is called a half adder. This type of circuit consists of an XOR gate and an AND gate connected in parallel. The diagram shows the layout of a half adder circuit.

The XOR produces the sum, and the AND gate produces the carry out signal. So looking at the possible calculations again, for 0+0, neither the XOR gate nor the AND gate are activated, and therefore the sum is 0 and there is no carry out bit (0). In both cases 0+1 and 1+0, the XOR gate activates and produces a 1 as the sum, whereas the AND gate remains inactive, so there is still no carry out bit (0). Only when 1+1 are added, the XOR gate produces a 0 as the sum, and the AND gate activates, so a 1 is produced as the carry out bit. If the bits from the next row left of the least significant bits should be added, there are now three possible inputs (X, Y, and carry), and therefore a half adder cannot be used as it would not take the carry bit from the first bits into consideration. A full-adder must be used, which is a different circuit.